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Evaluation of OpenMP for the Cyclops multithreaded architecture

機(jī)譯：為獨(dú)眼巨人多線程架構(gòu)評(píng)估Openmp

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Multithreaded architectures have the potential of tolerating large memory and functional unit latencies and increase resource utilization. The Blue Gene/Cyclops architecture, being developed at the IBM T. J. Watson Research Center, is one such systems that offers massive intra-chip parallelism. Although the BG/C architecture was initially designed to execute specific applications, we believe that it can be effectively used on a broad range of parallel numerical applications. Programming such applications for this unconventional design requires a significant porting effort when using the basic built-in mechanisms for thread management and synchronization. In this paper, we describe the implementation of an OpenMP environment for parallelizing applications, currently under development at the CEPBA-IBM Research Institute, targeting BG/C. The environment is evaluated with a set of simple numerical kernels and a subset of the NAS OpenMP benchmarks. We identify issues that were not initially considered in the design of the BG/C architecture to support a programming model such as OpenMP. We also evaluate features currently offered by the BG/C architecture that should be considered in the implementation of an efficient OpenMP layer for massive intra-chip parallel architectures.

機(jī)譯：多線程體系結(jié)構(gòu)具有容忍大內(nèi)存和功能單元延遲并提高資源利用率的潛力。 IBM T.J. Watson研究中心正在開發(fā)的Blue Gene / Cyclops體系結(jié)構(gòu)就是這樣一種提供大量芯片內(nèi)并行性的系統(tǒng)。盡管BG / C體系結(jié)構(gòu)最初是為執(zhí)行特定的應(yīng)用程序而設(shè)計(jì)的，但我們認(rèn)為它可以有效地用于各種并行數(shù)值應(yīng)用程序。當(dāng)使用基本的內(nèi)置機(jī)制進(jìn)行線程管理和同步時(shí)，為此非常規(guī)設(shè)計(jì)對(duì)此類應(yīng)用程序進(jìn)行編程需要大量的移植工作。在本文中，我們描述了CEPBA-IBM研究所目前針對(duì)BG / C正在開發(fā)的用于并行化應(yīng)用程序的OpenMP環(huán)境的實(shí)現(xiàn)。使用一組簡(jiǎn)單的數(shù)字內(nèi)核和NAS OpenMP基準(zhǔn)測(cè)試的一個(gè)子集評(píng)估環(huán)境。我們確定了在BG / C體系結(jié)構(gòu)設(shè)計(jì)中最初并未考慮的問題，以支持諸如OpenMP之類的編程模型。我們還評(píng)估了BG / C架構(gòu)當(dāng)前提供的功能，這些功能應(yīng)在大規(guī)模海量芯片內(nèi)部并行架構(gòu)的高效OpenMP層的實(shí)現(xiàn)中予以考慮。